1. Field of Invention
This invention relates to integrated circuit packaging and, more particularly, to multiple integrated circuits secured to a substrate and having a heat spreader thermally coupled to a surface of each of the integrated circuits opposite the surface to which the substrate is secured.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
An integrated circuit is generally manufactured by processing a topography of a wafer. Multiple processing steps take place in order to form circuitry across the processed surface. Following manufacture, individual die or chips are drawn from the wafer by slicing the wafer along the scribe line between neighboring die.
Each integrated circuit (i.e., die or chip) includes a series of input/output bonding pads arranged on the upper surface of the integrated circuit. The bonding pads can be arranged about a periphery of the integrated circuit or, alternatively, the bonding pads can be arranged in an array across the integrated circuit. If the bonding pads are placed near the periphery, fine metal wire can be used to connect the pads of the integrated circuit to leads of a package. The package serves to hermetically seal the integrated circuit, with electrical connectivity between the integrated circuit bonding pads and external leads of the package.
If the bonding pads are arranged in an array, then the integrated circuit can be inverted or “flipped” such that the array of bonding pads are connected to a corresponding array of a package substrate. The technique of bonding an inverted chip to a package substrate is oftentimes referred to as “flip-chip,” “C4,” or “ball grid array” bonding. On a surface of the package substrate opposite the flip-chips may also be an array of bonding pads similar to leads of a package. The end result, regardless of whether fine metal wires are used to form the connection or flip-chip bonding is used, is to present a packaged integrated circuit having a series of leads or receptors that can extend from the package for connection to a printed circuit board (PCB).
In instances where high-density connection is not needed, a packaged integrated circuit using wire bonds and, for example, a lead frame may be adequate. The leads extending from the hermitically sealed package can then be inserted into the PCB or, alternatively, the leads can be surface mounted using various solder reflow techniques.
In instances where a higher density connection is needed, however, flip-chip mounting may be more adequate. The integrated circuits are inverted, with an array of bonding pads mounted to a multi-layer package substrate (hereinafter referred to as “substrate”). The substrate may have many layers and serves to spread the contact array from a first density at the die to a second, lower density, at the opposing surface of the substrate. In most instances, there is a 1:1 correspondence between the electrical contact at the die and corresponding electrical contact at the PCB. By using multiple signal trace conductors, power planes, and ground planes within the substrate, a high-density spreader function is achievable using modern substrates.
Conventional flip-chip bonding mechanisms generally involve a single integrated circuit bonded to a substrate surface, with most if not all of the integrated circuit encapsulated with a curable fill material. In many applications, however, it is desirable to place a first integrated circuit in relative close proximity to a second integrated circuit. For example, it would be of benefit to place a core logic device of an execution unit near memory so that the parasitics on signals sent therebetween is reduced. Packaging each integrated separately (whether by flip-chip or wire-bonding) and then placing the individual packaged integrated circuits on a printed circuit board not only increases the parasitics, but also requires higher drive currents, higher power dissipation, more routing congestion, and leads to a larger overall size. Alternatively, the memory circuit might be integrated onto the same integrated circuit that embodies the logic device, for example. This, however, would lead to a relatively high lead time and design complexity of that integrated circuit, and result in a larger overall integrated circuit size. As the size increases, the overall yield might decrease.
It would be desirable to implement a package assembly that would accommodate multiple integrated circuits in order to reduce the parasitics, power dissipation, routing congestion, and size. By using a desired multiple chip or die package, the development costs and larger die sizes of attempting to place all of the multiple chip functionality on a single integrated substrate would also be reduced. In addition to deriving a multi-chip package, the desired package would also have better thermal characteristics by using an improved heat transfer mechanism. Still further, the desired multi-chip package could employ a mix-and-match assembly philosophy, whereby packaged and unpackaged integrated circuits can be accommodated with optimal heat transfer from each.